Rigid Pipeline

From Lyra

This example models a rigid pipeline stage.

module rp_stage(in<int> enq, out<int> deq)
{
    reg int myreg;

    init                                                      
    {
        myreg = 0;
    }

    fsm my_fsm                                                
    {
        init S:
            when (enq, deq)
            {
                /* enqueue and dequeue occurs simultaneously 
                    => pipelined transfer */
                deq.write(myreg);
                myreg = enq.read();
                goto S;
            }
    }
}

module producer(out<int> produce)
{
    reg int myreg;

    init
    {
        myreg = 1;
    }

    fsm my_fsm
    {
        init U: // start state
            when (produce)
            {
            // rendezvous to synchronize with and forward data to buffer
                produce.write(myreg);
                myreg = myreg + 1;
                goto U;
            }
    }
}

module consumer(in<int> consume)
{
    reg int myreg;

    init
    {
        myreg = 0;
    }

    fsm my_fsm
    {
        init X: // start state
            when (consume)
            {
                // rendezvous to synchronize with and receive data from buffer
                myreg = consume.read();
                goto X;
            }
    }
}

                                                              
module toplevel
{

    /* two rendezvous, point to point */                      
    rendv p1, p2, p3, p4, p5;

    /* instantiation of modules */                            
    rp_stage s1(p1, p2);
    rp_stage s2(p2, p3);
    rp_stage s3(p3, p4);
    rp_stage s4(p4, p5);

    producer pro(p1);                                         
    consumer con(p5);
}